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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:39:01 10/13/2009 
-- Design Name: 
-- Module Name:    regfile - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity regfile is
    Port ( rs : in  STD_LOGIC_VECTOR (4 downto 0);
					rt : in  STD_LOGIC_VECTOR (4 downto 0);
					rd : in  STD_LOGIC_VECTOR (4 downto 0);
           wrdata : in  STD_LOGIC_VECTOR (31 downto 0);
           regwrite : in  STD_LOGIC;
           reg1 : out  STD_LOGIC_VECTOR (31 downto 0);
           reg2 : out  STD_LOGIC_VECTOR (31 downto 0);
			  clock : in  STD_LOGIC);
end regfile;

architecture Behavioral of regfile is

  type rf_type is array (0 to 31) of 
        std_logic_vector(31 downto 0);
  -- rf_type : banco de 32 registros de 32 bits c/u	  
  
  signal tmp_rf: rf_type;

begin

  write: process(clock, rd, regwrite)
  -- Si esta habilitada la escritura por regwrite=1 
  -- se mueve el dato que esta en wrdata al registro direccionado por rd
  begin
	if (clock'event and clock = '1') then
	  if regwrite='1' then
	    tmp_rf(conv_integer(rd)) <= wrdata;
	  end if;
	end if;
  end process;						   
	
  read1: process(clock, regwrite, rs)
  -- Si esta habilitada la lectura por regwrite=0 
  -- se mueve el dato que esta en registro direccionado por rs a reg1(A)
  begin
	if (clock'event and clock = '1') then
	  if regwrite='0' then								 
	    reg1 <= tmp_rf(conv_integer(rs));
	  end if;
	end if;
  end process;
	
  read2: process(clock, regwrite, rt)
  -- Si esta habilitada la lectura por regwrite=0 
  -- se mueve el dato que esta en registro direccionado por rt a reg2(B)
  begin
	if (clock'event and clock = '1') then
	  if regwrite='0' then								 
	    reg2 <= tmp_rf(conv_integer(rt));
	  end if;
	end if;
  end process;

end Behavioral;

